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Inter Quad Synchronization System for Modular Processing Systems

IP.com Disclosure Number: IPCOM000079575D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

deMilt, MD: AUTHOR

Abstract

In a modular processing system (MPS), where several processors (QUADS) share a common bus to main memory, synchronization must be provided to establish priorities for broadcast and memory access. Each QUAD has storage control logic which keeps track of its own bus priority relative to the other QUADS by using two 4-state priority clocks, which must start simultaneously in every QUAD for each to be able to tell what the system priority is at any instant.

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Inter Quad Synchronization System for Modular Processing Systems

In a modular processing system (MPS), where several processors (QUADS) share a common bus to main memory, synchronization must be provided to establish priorities for broadcast and memory access. Each QUAD has storage control logic which keeps track of its own bus priority relative to the other QUADS by using two 4-state priority clocks, which must start simultaneously in every QUAD for each to be able to tell what the system priority is at any instant.

The basic timing sequence in each QUAD is governed by an 8-state ring counter with a 120ns cycle time, driven by a 15/15ns clock which starts the rings in integer multiples of 30ns. Additionally, there is a 960ns counter to track the main memory cycle and a 15,360ns counter to track the interunit memory access priority rotation.

Depending on the state the system is in, a QUAD will synchronize in one of the following three modes:

1. Clear (reset) and Restart (CAR). When no other QUAD is enabled, a single QUAD may be enabled by a straight forward reset and restart of its timing rings.

2. Clear, Listen, and Restart (CLR). When at least one other QUAD is running, the timing rings of the QUAD being enabled remain quiescent after reset until receipt of an external sync signal from the running QUAD. The timing signals are then started at T(o). The electrical delay between QUADS must be calculated, and the sync transmitted that much earlier than T(o) for the...