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Bidirectional Interface Data Transfer Registers

IP.com Disclosure Number: IPCOM000079583D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

McCarthy, JH: AUTHOR [+2]

Abstract

Data is automatically serialized/deserialized between data processing devices having differing bit handling interfaces. Three registers are employed, so as to reduce the number of interrupts to the main processing equipment while increasing the amount of available processing time, by relieving the controlling equipment of transfer control tasks.

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Bidirectional Interface Data Transfer Registers

Data is automatically serialized/deserialized between data processing devices having differing bit handling interfaces. Three registers are employed, so as to reduce the number of interrupts to the main processing equipment while increasing the amount of available processing time, by relieving the controlling equipment of transfer control tasks.

In the example shown, data is transferred between a main processing unit 10 such as a direct control channel or CPU interface and an I/O device 11, through interfacing attachment adapter 12. Unit 10 transfers word or double-byte output data on bus-out 13 and receives word width data on bus-in 14. Interface registers 15, 16 and 17 each are less than a word wide. For a double-byte word at the 13 and 14 busses, 15, 16 and 17 are each typically one-byte wide. Registers 15 and 16 directly receive the two-byte word present from bus-out 13 and with register 17, provide a path to transfer data on a byte-wide interface through I/O bus-in 18. When transferring data from 10 to 11, data is first loaded into X register 15 and Y register 16 from the word present on 13 as transferred through AND 19, when enabled by signals on 20.

Command and mode decode circuit 21 enables out control 22 via mode control 23, so that the contents of 15 is immediately gated through translate circuit 24 to I/O bus-in 18. Various I/O devices may require data translation between internal CPU code and its specific data handling code. An example might be a card reader for unit 11 using 6-bit card code interfacing to an 8-bit EBCDIC CPU at 10. Activation of translate circuits 24 and 28 is controlled by mode control 23.

Most devices will not require translate circuits 24 and 28. The contents of Y register 16 are concurrently transferred to Z register 17 and subsequently transferred to 18, after 11 has accepted the byte from 15. That is, control unit 10 provides a command on 13, to enable 12 via 21 with...