Browse Prior Art Database

Electrically Rewritable Nonvolatile Storage having Reduced Write Voltage

IP.com Disclosure Number: IPCOM000079587D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

James, RP: AUTHOR

Abstract

This device utilizes a stack floating gate/control gate structure. Hot carrier emission from depleted regions parallel to the surface are used for storing a charge on the floating gate. This reduces the write volume greatly, increases reliability, reduces the area occupied by peripheral circuitry, and limits the need for an additional power supply.

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Electrically Rewritable Nonvolatile Storage having Reduced Write Voltage

This device utilizes a stack floating gate/control gate structure. Hot carrier emission from depleted regions parallel to the surface are used for storing a charge on the floating gate. This reduces the write volume greatly, increases reliability, reduces the area occupied by peripheral circuitry, and limits the need for an additional power supply.

Electrically rewritable nonvolatile silicon storage is required for user- inaccessible control which can be modified in the machine, and also for nonvolatile read/write storage in small machines where core or disk is costly. The storage cell depicted schematically in Fig. 1 embodies a field-effect transistor (FET) with a floating gate 12 that can be positively charged and uncharged. To write either charge state on the floating gate 12, the read/write line 14 is biased to -10 volts and the column metal address line 16 is negatively biased to turn device 18 on. In the selected cell, the source 28 of 10 goes negative until breakdown occurs. Current limiting is provided by the channel resistance of device 18. If it is desired to put a positive charge on the floating gate 12, column metal address line 20 is biased to -10 volts. Assuming the floating gate 12 is initially charged; a conductive channel will form between the source 28 of device 10 and the P+ layer 24 of the P+ -N region, as shown most clearly in Fig. 3. Fig. 3 is taken on line 3-3 of Fig....