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Browse Prior Art Database

Preventing Surface Inversion Under Thick Oxide of N Channel IGFET's

IP.com Disclosure Number: IPCOM000079592D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Shepard, JF: AUTHOR

Abstract

Leakage currents in field-effect transistor (FET) devices made possible by inversion regions produced under the thick oxide areas (areas of a chip not used for active devices) of the device are a problem, which results in device failure using known FET fabrication techniques.

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Preventing Surface Inversion Under Thick Oxide of N Channel IGFET's

Leakage currents in field-effect transistor (FET) devices made possible by inversion regions produced under the thick oxide areas (areas of a chip not used for active devices) of the device are a problem, which results in device failure using known FET fabrication techniques.

Surface inversion under the thick oxide resulting in leakage currents may be prevented, by incorporating a region of polycrystalline silicon within the thick oxide region of the field-effect transistor device. The polycrystalline region within the SiO(2) can exhibit a negatively charged state. The negative charge of the polycrystalline region is utilized to produce positive charges on the surface of an underlying semiconductor substrate, which has previously been rendered negatively charged by the presence of positive charge in the oxide after the sputtering of a final SiO(2) passivation layer.

The structure shows a field-effect transistor 1 having source and drain 2 and 3, respectively, and a gate 4 spaced from the surface of a semiconductor substrate 5 by a thin oxide layer 6. Thick oxide regions 7 cover the surface of substrate 5 everywhere, except at thin oxide regions 6 and contact regions 8. Polycrystalline regions 9 which are utilized to provide a negatively charged region are formed on the surface of thick oxide 7 everywhere, except at the contact, thin oxide and gate regions. Finally, a layer 10 of sputtered SiO(2) is deposited over FET 1 and polycrystalline regions 9.

As shown, regions 9 have a negative charge which induce positively charged regions at the surface of substrate 5. The positive charges at the surface of subst...