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Structure for the Passivation of Semiconductor Chips

IP.com Disclosure Number: IPCOM000079603D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Cook, HC: AUTHOR [+4]

Abstract

The presence of pinhole defects in passivation layers for integrated circuits may be counteracted by providing two passivating layers over surfaces to be passivated, using different insulator materials for the two passivation layers, and defining each by separate photoresist operations using different masks. Shown is a portion of a silicon substrate 10 forming a part of an integrated circuit. Substrate 10 has metal land 12 on its surface in a desired pattern. While metal land 12 may be any conducting metal, this structure is particularly useful with silver, molybdenum, or other metal susceptible to corrosion. Over metal land 12 is provided a first insulation layer 14 and a second insulation layer 16.

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Structure for the Passivation of Semiconductor Chips

The presence of pinhole defects in passivation layers for integrated circuits may be counteracted by providing two passivating layers over surfaces to be passivated, using different insulator materials for the two passivation layers, and defining each by separate photoresist operations using different masks. Shown is a portion of a silicon substrate 10 forming a part of an integrated circuit. Substrate 10 has metal land 12 on its surface in a desired pattern. While metal land 12 may be any conducting metal, this structure is particularly useful with silver, molybdenum, or other metal susceptible to corrosion. Over metal land 12 is provided a first insulation layer 14 and a second insulation layer 16. A desired characteristic of the second layer 16 is that it be subject to attack by an etchant which does not attack the first layer 14 to an appreciable extent.

In the course of forming the insulation layers 14 and 16, pinhole defects 18 and 20, respectively, are formed in the layers. Using separate photoresist application and different masks to define the insulation layers, access to the metal land through the pinholes is prevented.

In a specific example, sputtered SiO(2) is used as the first passivating layer
14. To define via holes, not shown, down to metal land 12, photoresist is applied to the sputtered SiO layer, the photoresist is exposed and developed, and etching is carried out with hydrofluoric acid. Poly...