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Leakage Tolerance Improvement

IP.com Disclosure Number: IPCOM000079604D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Gersbach, JE: AUTHOR

Abstract

Cascade current-switch circuits used in logic and memory functions can be modified to tolerate leakage currents caused by defects in wafer processing, by coupling a diode to the output leg of the first current switch.

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Leakage Tolerance Improvement

Cascade current-switch circuits used in logic and memory functions can be modified to tolerate leakage currents caused by defects in wafer processing, by coupling a diode to the output leg of the first current switch.

The circuit shown in the figure is a cascade current-switch circuit useable in logic and memory functions. When the voltage, at terminal 10, is large, relative to the forward voltage drops of the transistors T1 and T2, and the output transistor T3 is held in the off condition for long periods of time, the output node,
i.e., the emitters of transistors T1 and T2, will rise to the level of the input 10 and the parasitic capacitance CX of the output of transistors T1 and T2 becomes charged to the level of input 10. Thus, when transistor T3 turns on, the parasitic capacitance, CX, becomes discharged through T3 prior to either transistor T1 or T2, turning on, causing a false output to occur.

This problem is ended, however, by coupling a diode, D1, between the collector of transistor T3 and a voltage source V1. Thus, as leakage occurs across either transistor T1 or T2, and the parasitic capacitance of the output increases, the diode D1 prevents the emitter node of transistors T1 and T2 from ever charging substantially above the reference voltage applied to the anode of diode D1. Thus, the time delay increase when T3 becomes conductive, is held to a minimum and is substantially independent of defects in transistors T1 and T2....