Prewire Prediction Model
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Hill, CP: AUTHOR [+4]
A method is shown for determining early in the development stages of a data-processing system, the likelihood of success in electrically interconnecting the pins of a substructure (component). The substructure 10 (Figs. 1-3) is mounted on a structure 11, and the pins 14 are interconnected by printed wires 12 embedded in a plurality of planes in the structure and by vias 13 (plated-through holes) electrically interconnecting wires of different planes.
Prewire Prediction Model
A method is shown for determining early in the development stages of a data-processing system, the likelihood of success in electrically interconnecting the pins of a substructure (component). The substructure 10 (Figs. 1-3) is mounted on a structure 11, and the pins 14 are interconnected by printed wires 12 embedded in a plurality of planes in the structure and by vias 13 (plated- through holes) electrically interconnecting wires of different planes.
The method includes the steps of selecting a group of parameters which are available and defined early in the development stages, and which are related to the determination of line count capacity (LC CAP), line count demand (LC DEM) and the capacity-demand ratio (CDR). The parameters are used to calculate the line count capacity, the line count demand, and the capacity-demand ratio. The values of the line count capacity, line count demand and capacity-demand ratio are then used to calculate PPM (the predicted number of pins on the substructure which can be successfully interconnected by the printed wiring and vias).
The value of PPM and the total number of pins on the substructure are used to determine the percent success of wiring a minimum length, and to predict connection failures and the percent success to complete the connections attempted, for both the local (substructure) wirability and the matrix (multisubstructures) wirability cases. These steps can be repeated for each of several hardware levels of a package, e.g. chip-module, module-card, card-board. Desired parameters can be selected from the following list, which covers the general cases (additional parameters may be added as special cases occur): 1. Total pins per Component (TMP). 2. Average "Signal" Pins Used per Component (SPU). 3. Width of Component in Channels (WMC). WMC = (No. channels between extreme component pins) + 1,
where a channel is the space between adjacent pins, if so
defined by item 17.
4. Length of Component in Channel (LMC).
5. Maximum "Signal Pins" Wired per Component (MPU).
6. Average Component Perimeter Pins (CPP).
7. Number of X-Y Planes (having both N and Y lines on same
8. Lines per Channel in X Direction (LPCX).
9. Lines per Channel in Y Direction (LPCY).
10. Number of X Planes (having X lines only) (PX).
11. Number of Y Planes (having Y lines only) (PY).
12. Width of Component Matrix (N), the number of components in
wiring structure array in the N direction.
13. Length of Component Matrix (M), the number of components in
wiring structure array in M direction.
14. Average Number of Pins per Net (PPN), the total number of
pins to wire divided by total number of nets to wire, >/-2.
15. Width of Wiring Structure in Length Units (WC).
16. Length of Wiring Structure in Length Units (LC).
17. basic Pitch in Length Units (WP), the basic wiring grid;
this defines a channel.
18. I/O (Input/Output) Edges for N (IONE).
Choices: 0 (e.g., area array)