Browse Prior Art Database

Matched Expansion Chip Package

IP.com Disclosure Number: IPCOM000079617D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 20K

Publishing Venue

IBM

Related People

VanVestrout, VD: AUTHOR

Abstract

This is a chip packaging arrangement utilizing matched expansion materials and adapted to facilitate assembly and rework operations. A silicon chip 10 is backbonded to an invar or KOVAR* plate 11 by a relatively low-melt solder 12. Plate 11 is, in turn, bonded to a substrate 13 with a filled or unfilled epoxy conductive or nonconductive material 14. The substrate 13 material could be copper, epoxy glass, ceramic, or the like, depending upon the packaging application.

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Matched Expansion Chip Package

This is a chip packaging arrangement utilizing matched expansion materials and adapted to facilitate assembly and rework operations. A silicon chip 10 is backbonded to an invar or KOVAR* plate 11 by a relatively low-melt solder 12. Plate 11 is, in turn, bonded to a substrate 13 with a filled or unfilled epoxy conductive or nonconductive material 14. The substrate 13 material could be copper, epoxy glass, ceramic, or the like, depending upon the packaging application.

The silicon chip lO to invar 11 bond with a low-melt solder 12 provides a reliable joint, having a very close coefficient of expansion match between the invar and silicon. Accordingly, the backbond will not be overstressed by a thermal cycling of the package. The filled or unfilled epoxy joint between the plate 11 and substrate 13 provides a reliable viselastic joint, particularly from a stress standpoint, since at elevated temperatures it will not crack due to the coefficient of expansion mismatch between the substrate material 13 and the invar plate 11.

If a relatively low heat transferring material were used for the substrate 13, a heat sink device may be incorporated in the invar-to-substrate joint to increase heat dissipating capabilities of the package.

This packaging arrangement is particularly well adapted to accommodate large sized or area array type chips. The chip-to-substrate interconnections can be by wire bonded, C4, or decal technologies which have become...