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Addressing a Second Page of Registers Without Increasing the Register Field Length

IP.com Disclosure Number: IPCOM000079626D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Stevens, KW: AUTHOR

Abstract

The described second page addressing concept is particularly useful in a computer having the following design constraints: 1) Maximum instruction lengths of 16 bits; 2) An immediate field of not less than eight bits; 3) A memory word size of 16 bits; 4) More than eight full-word registers addressable at eight-bit byte boundaries; and 5) The length and location of all instruction fields selected so as not to cross eight-bit boundaries.

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Addressing a Second Page of Registers Without Increasing the Register Field Length

The described second page addressing concept is particularly useful in a computer having the following design constraints: 1) Maximum instruction lengths of 16 bits;

2) An immediate field of not less than eight bits;

3) A memory word size of 16 bits;

4) More than eight full-word registers addressable at

eight-bit byte boundaries; and

5) The length and location of all instruction fields

selected so as not to cross eight-bit boundaries.

Two separate pages of registers, each containing eight full-word registers, and each page being located anywhere in a plural page register storage can be addressed by the use of a page bit located in various unused bit positions, which become available within an instruction format as the result of the operation specified by the OP code. The page bit, or its absence which indicates the default page, points to a page pointer register, the contents of which identifies the page within which operand registers are located.

To meet the above design constraints, immediate-to-register instructions require all bit positions without redundancy and, therefore, can only be performed using a single default page of registers. For half-word (eight bits) register-to- register operations, the eight-bit immediate field is not needed and therefore the remaining eight bits are available for other purposes. Inasmuch as the immediate OP code was only four bits, additional instructions operating on registers located either in a default page or in a second page can be specified, using two additional OP code modifier bits yielding a total OP code field of six bits. The two remaining bit positions labeled 22 and 24 can then be used to select either a default or a second page pointer register, the contents of which identify the page within which registers R1 or R2 are located, respectively. For example, a 0 bit could indicate the default page pointer register and a 1 bit could indicate the second page pointer register.

When executing instructions involving a full word such as instructons involving a memory address which is a full 16-bi...