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Synchronizer for Valid Distorted Periodic or Aperiodic Data

IP.com Disclosure Number: IPCOM000079655D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Brandner, JM: AUTHOR [+2]

Abstract

Synchronizing circuitry is provided for synchronizing a data line and a clock line whereby the strobing edge of the clock is centered relative to valid undistorted data, or comes within valid distorted data with distortion up to 47 per cent. The valid distorted data can be periodic or aperiodic.

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Synchronizer for Valid Distorted Periodic or Aperiodic Data

Synchronizing circuitry is provided for synchronizing a data line and a clock line whereby the strobing edge of the clock is centered relative to valid undistorted data, or comes within valid distorted data with distortion up to 47 per cent. The valid distorted data can be periodic or aperiodic.

The clock period Tc is divided into 32 intervals. Oscillator 10 provides pulses for advancing counter 20 which divides the frequency by 32. The clock period Tc is divided into five zones, as shown in Fig. 2. When the signal on data line 30 rises, the clock zone is examined and appropriate corrections, if any, are made as indicated in Fig. 3. The appropriate corrections are provided by correction control circuit 40.

In Fig. 4 the data is 1,0,.., but is initially strobed as 1, 1, .. . Under this condition, the signal on data line 30 rises in zone 5. Thus, the clock is retarded 1/16 and a sequence of corrections will be made, whereby the clock will be in synchronization with data and the data will be strobed as 1, 0, ...

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