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Method to Analyze the Wirability of Weinberger Chips

IP.com Disclosure Number: IPCOM000079661D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 93K

Publishing Venue

IBM

Related People

Hanan, M: AUTHOR [+3]

Abstract

The cost of determining the actual wiring patterns for a "Weinberger" chip is high in terms of manpower and/or computer time. The method described herein enables the designer to estimate the wirability of a chip design before actual wiring is attempted. Prior to allocating an expenditure of time and effort in an attempt to wire an "unwirable" chip, the designer can change the logic on that chip or change the size, shape or geometry of the chip to yield a wirable chip.

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Method to Analyze the Wirability of Weinberger Chips

The cost of determining the actual wiring patterns for a "Weinberger" chip is high in terms of manpower and/or computer time. The method described herein enables the designer to estimate the wirability of a chip design before actual wiring is attempted. Prior to allocating an expenditure of time and effort in an attempt to wire an "unwirable" chip, the designer can change the logic on that chip or change the size, shape or geometry of the chip to yield a wirable chip.

The figure provides a stylized diagram of a field-effect transistor (FET) chip. The upper-left portion shows that the periphery of the chip contains 48 pins (actually wire bonding pads) used for interchip connection. Although there are 48 total pins, 5 are used for power and ground so that only 43 signal pins are available for interchip connections. Power and ground buses geometrically divide the interior of the chip into 4 columns, as shown; this imposes a horizontal coordinate system on (the plan view of) the chip. A vertical coordinate system is obtained by vertically subdividing each column into 94 cells. A cell is the smallest geometric area which can define the position of a circuit (or part thereof).

The lower portion of the figure provides a detailed plan view of several adjacent cells and includes wiring detail. Wiring is done both above and below the oxide. Most intracolumn wiring is done vertically above the oxide layer with the aluminum wire...