Browse Prior Art Database

Read Only Storage Branch Control

IP.com Disclosure Number: IPCOM000079662D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Dym, H: AUTHOR [+4]

Abstract

A data-processing machine includes microinstructions in a conventional type of read-only storage memory (ROS), which includes an address register ROSAR and a data register ROSDR. Initially a macroinstruction loads high-order bits into ROSAR. Then until a microinstruction sequence has been completed, the ROS provides its own next addresses from a conditional field (CF) and unconditional field (UF).

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Read Only Storage Branch Control

A data-processing machine includes microinstructions in a conventional type of read-only storage memory (ROS), which includes an address register ROSAR and a data register ROSDR. Initially a macroinstruction loads high-order bits into ROSAR. Then until a microinstruction sequence has been completed, the ROS provides its own next addresses from a conditional field (CF) and unconditional field (UF).

Field UF supplies the address for ROSAR bits 2-5 always and bits 0, 1, if field CF has a predetermined value, e.g., all 0's or all 1's, with Sits 0, 1 set by the UF field data, e.g., using the same data for bits 0 and 1 as the data for bits 2 and 3, respectively, which saves data positions in ROS by requiring only one permutation of the CF field to switch quadrants. The CF field feeds into the conditional field decoder for which there are 16 permutations, the first four of which decimal 0-3 and 15 also are unconditional branch values of which all control bit positions 6 and 7, and 15 controls the quadrant switch also.

The other 11 permutations are conditional branch values, only one of which can be selected by the CF field at a time to test conditions on external Lines, to provide the appropriate conditional values in bit positions 6 and 7 at time T4. The ROSAR bit positions 2-7 are reset at time T2 on each cycle. The ROSAR is set at time T1 during load time. Bit positions 0 and 1 are modified by a quadrant switch value from field CF in...