Browse Prior Art Database

Priority Determination and Servicing of I/O Devices

IP.com Disclosure Number: IPCOM000079675D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Birch, FT: AUTHOR [+6]

Abstract

In Fig. 1, a data-processing system includes several I/O devices 13 connected to a central processor 29 by a bus 30, with plural data lines 11 and plural control lines 24. A priority control system sequentially addresses specific I/O devices 13 requesting service to be provided, according to a predetermined priority. A control 10 assigns data lines 11 to a service request register 12 during a polling interval. One unique data line 11 is assigned to each I/O device 13 to be serviced at a particular priority level.

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Priority Determination and Servicing of I/O Devices

In Fig. 1, a data-processing system includes several I/O devices 13 connected to a central processor 29 by a bus 30, with plural data lines 11 and plural control lines 24. A priority control system sequentially addresses specific I/O devices 13 requesting service to be provided, according to a predetermined priority. A control 10 assigns data lines 11 to a service request register 12 during a polling interval. One unique data line 11 is assigned to each I/O device 13 to be serviced at a particular priority level.

A data requesting transmitter 25 in I/O device 13 places a 1 bit on each data line 11 for which an I/O device 13 is requesting service. Register 12 stores the bits representing priority levels of I/O data lines 11 when used as service request lines, adjacent hits being in descending order of priority which will be applied in providing service. Logic 19 converts the number of leading 0's in register 12 to a binary number, representing the address of the highest priority I/O device 13 requesting service.

A processor control 14 enables the processor 15 to provide the addressed I/O device 13 with the service requested from processor functional unit 15 via gate 22 and line 23, gating the address via gate 20 and line 21 to lines 11, and signals the conclusion of service on line 16. Logic 17 responsive to the conclusion-of-service signal on line 16 replaces the highest level binary 1 in the service request register with a 0. A control 18 responsive to logic 17 signalling replacement, causes the repetition of operation by processor control 14 for a number-of-leading-0's to address conversion and I/O device servicing, until all I/O devices requesting service during polling interval have been serviced.

The role of the bit levels can be reversed by storing 0 bits, counting leading 1's, etc.

I/O interrupt works in two steps when there are several devices on any given interrupt level, as shown in Fig. 2. (1) The I/O bus 40 of lines 11 is examined to see on which of its data lines 0 - 7 have signal levels which are up or on. There may be several devices requesting service on any given level 0 - 7. Determination of the highest requesti...