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Self Contained Instruction Counter for Digital Computers

IP.com Disclosure Number: IPCOM000079676D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Carlton, T: AUTHOR [+4]

Abstract

The buffer address register (BAR) stores the current memory address of the instruction which a data-processing machine is executing at the present moment, and calculates the next sequential instruction address. The BAR has 3 registers, R1, R2, R3, each the same number of bits wide, parallel in-parallel out. R1 holds the present address. R2 has a "copy" of data in R1 so that the ripple through adder in the BAR can calculate the next sequential address. R3 stores the present address at the beginning of a CYCLE STEAL OPERATION, so that the machine can return to the proper place in memory when the CYCLE STEAL operation is finished.

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Self Contained Instruction Counter for Digital Computers

The buffer address register (BAR) stores the current memory address of the instruction which a data-processing machine is executing at the present moment, and calculates the next sequential instruction address. The BAR has 3 registers, R1, R2, R3, each the same number of bits wide, parallel in-parallel out. R1 holds the present address. R2 has a "copy" of data in R1 so that the ripple through adder in the BAR can calculate the next sequential address. R3 stores the present address at the beginning of a CYCLE STEAL OPERATION, so that the machine can return to the proper place in memory when the CYCLE STEAL operation is finished.

Register R1 has associated first, second, and third input gates G1, G2, G3 for selectively storing a current instruction address therein from one of three address sources.

The adder selectively increments the contents of register R2 by a predetermined number of counts.

Gate G1 controls the flow of data fron an external address source for initializing an instruction routine, or for radically changing an instruction address to perform a branch or interrupt. Gate G2 controls the flow of data from the output of R2 modified by the adder to step (increment) to the next instruction. G3 controls the flow of data from R3 to R1 after an interrupt or CYCLE STEAL OPERATION, to restore normal instruction processing to perform the next instruction which was to have been performed prior to the inte...