Browse Prior Art Database

Multiple Device Processor Interface

IP.com Disclosure Number: IPCOM000079680D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Dosch, DL: AUTHOR [+4]

Abstract

A single communication register is used by the processor side of an interface between a number of devices and a processor to pass control information, device identification and data, to the device side of the interface. The same register is used by the device side to pass control information, device identification, data. device status and device sense bits to the processor side of the interface.

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Multiple Device Processor Interface

A single communication register is used by the processor side of an interface between a number of devices and a processor to pass control information, device identification and data, to the device side of the interface. The same register is used by the device side to pass control information, device identification, data. device status and device sense bits to the processor side of the interface.

One bit (I) of the communication register is used to force the processor to interrogate the communication register. Other bits (ID) of the register are defined as device identification bits. These bits indicate to which device the interface is currently dedicated. If k bits are defined for device identification, then 2/k/-1 devices can be attached. One state of the ID is reserved to indicate that the interface is available.

The remaining bits of the communication register are interpreted by each device as control, data, status, and sense as required. The control information includes an indication width of the data path currently in use. The interpretation of the communication register is a function of the device identification bits and of the current state of the addressed device.

Two latches A and B are set and reset by the device side of the interface and interrogated by both sides, to reserve the communication register and provide an interlock between sides. Latch A allows the processor side of the interface to reset the register, bu...