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Reduced Image Data Generator

IP.com Disclosure Number: IPCOM000079693D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Brookman, JW: AUTHOR

Abstract

Logic circuitry is shown for reducing the resolution of images made from black-white bits. The reduction is accomplished by allowing decoding all possible bit patterns and providing a switch for each such bit pattern. The switch settings determine whether each pattern, when encountered, generates a black or white bit comprising the reduced data. The switches thus comprise a selective weighting of the original bit patterns.

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Reduced Image Data Generator

Logic circuitry is shown for reducing the resolution of images made from black-white bits. The reduction is accomplished by allowing decoding all possible bit patterns and providing a switch for each such bit pattern. The switch settings determine whether each pattern, when encountered, generates a black or white bit comprising the reduced data. The switches thus comprise a selective weighting of the original bit patterns.

In the example, Fig. 1 illustrates the 16 possible bit patterns in a 4-bit matrix. Fig. 2 illustrates the decoding of the bit patterns by the logic of Fig. 3, to generate a signal on the one of sixteen output lines representing the decoded bit pattern. Fig. 4 illustrates the logic circuitry 10 of Fig. 3, that provides the generated output signal to one of the switches 11, Which may, depending upon its setting, supply the signal to OR circuit 12 to generate the reduced data on line 13.

The specific weighting selected in the example comprises patterns 2Y3 and 1Y3 in module 1 and 2Y3, 1Y0, 1Y1, 1Y2 and 1Y3 in module 2. These are indicated by the adjacent X in Fig. 1.

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