Browse Prior Art Database

Video Data Display Flagwave Eliminator

IP.com Disclosure Number: IPCOM000079697D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Popick, SJ: AUTHOR [+2]

Abstract

In a video display such as a television or video monitor, a "flagwaving" display distortion is caused by electromagnetic radiation, both internal and external to a video display enclosure, which is asynchronous with the rate at which the signal source scans the video picture. The conventional to a video display enclosure, which is asynchronous with the rate at which the signal source scans the video picture. The conventional solution to the "flagwaving" problem is the use of MU metal shielding around the source of radiation including, if necessary, the cathode-ray tube itself. This represents a relatively expensive solution to the problem, particularly for a low-cost display terminal.

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Video Data Display Flagwave Eliminator

In a video display such as a television or video monitor, a "flagwaving" display distortion is caused by electromagnetic radiation, both internal and external to a video display enclosure, which is asynchronous with the rate at which the signal source scans the video picture. The conventional to a video display enclosure, which is asynchronous with the rate at which the signal source scans the video picture. The conventional solution to the "flagwaving" problem is the use of MU metal shielding around the source of radiation including, if necessary, the cathode-ray tube itself. This represents a relatively expensive solution to the problem, particularly for a low-cost display terminal.

An electronic solution to "flagwaving" distortion utilizes a phase-locked loop linear integrated circuit 2O, the inputs and outputs of which are shown as pins 1- 16. The phase-locked loop module 2O contains a voltage-controlled oscillator and a phase comparator. The voltage-controlled oscillator is adjusted to the desired free-running frequency by capacitor 17, resistors 19, 21 and rheostat 23 which are connected to pins 5, 6.

A reference frequency f(1) REF comprising the voltage-controlled oscillator frequency divided by a constant, is applied from input terminal 25 to pin 15 of the phase-locked loop module 20; and a second reference frequency f REF comprising the line frequency is applied from terminal 27 to pin 12. These two frequencies are...