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Transparent Refreshing for Semiconductor Dynamic Random Access Memory

IP.com Disclosure Number: IPCOM000079705D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 4 page(s) / 41K

Publishing Venue

IBM

Related People

Gerardin, CJ: AUTHOR [+2]

Abstract

In a dynamic metal-oxide semiconductor (MOS) memory, data is stored in cells arranged in rows and lines, each cell being provided with capacitors that discharge as a function of time. Some time after storage, say 2 ms, the charge is totally erased unless data is refreshed before.

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Transparent Refreshing for Semiconductor Dynamic Random Access Memory

In a dynamic metal-oxide semiconductor (MOS) memory, data is stored in cells arranged in rows and lines, each cell being provided with capacitors that discharge as a function of time. Some time after storage, say 2 ms, the charge is totally erased unless data is refreshed before.

Memory operates in either of two modes. Memory is accessed by ALU; refreshing must not prevent the access from being executed. Memory is thus split in two parts I and II which are alternatively accessed by ALU or refreshed, refreshing taking place in one part while accessing takes place in the other part. Any access to a part is associated with a refreshing in the other part.

Memory is in a standby mode. No access to memory is made by ALU and a compulsory refreshing must be made before erasure of data.

A refreshing cycle is made of two periods of time T1 and T2 with T1 being of a given time duration, and with T2 corresponding to a period of variable duration,
i.e., varying between zero and 2/3 of a ms in the example under consideration, as it will be hereunder explained.

Each part I and II is provided with a refreshing counter 1, 2, which is in the "0" state at the beginning of a refreshing cycle, i.e., at the beginning of period T1. Each refreshing increments the counter of the part being refreshed by +1. Count of counters 1 and 2 is also an address for the sequential accessing to lines of parts I and II. Switching circuits 3 and 4 connect parts I and II, either to ALU or to counters 1 and 2. They are controlled by control units 5 and 6, respectively, that provide the +1 increment to counters 1 and 2. Control units also receive a control signal from ALU, which signal indicates which of both circuits associated with parts I and II are implied in refreshing the parts.

Refreshing occurs in one part as ALU accesses the other part. When counters 1 and 2 have reached their maximum count, as detected by detector 7 or detector 8 within period T1 as determined by counter 11, no further refreshing takes place in corresponding part I or II during period T1.

At the end of period T1, the count of counters 1 and 2 is examined. Since the counts are maximum at this instant, there is no period T2 and a new refreshing cycle starts with period T1. In such a mode of operation of the memory, refreshing does not prevent ALU from accessing memory; refreshing is said to be transparent.

When memory is in the standby mode, it is not accessed by ALU and no systematic refreshing is made in memory accordingly.

At the beginning of a refreshing cycle, counters 1 and 2 are in their 0 state. At the end of period T1, they have not incremented their count. This is interpreted as a requirement for a compulsory refreshing. Detector 12 examines the count of counters 1 and 2 through OR circuit 9 connected to detectors 7 and
8. Detector 12, under control of circuitry 10, controls refreshing circuitry 13, the

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