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Cross Coupled True and Complement Powering Circuit

IP.com Disclosure Number: IPCOM000079739D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Lee, JM: AUTHOR [+2]

Abstract

This 3s a cross-coupled true and complement powering circuit, for driving highly capacitive loads with minimal loading at the input.

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Cross Coupled True and Complement Powering Circuit

This 3s a cross-coupled true and complement powering circuit, for driving highly capacitive loads with minimal loading at the input.

Fig. 1 illustrates the cross-coupled powering latch, including cross-coupled field-effect transistors T3 and T4 and gateable load transistors T1 and T2. Unlike conventional latches where the impedance of the load transistors T1 and T2 is much higher than the active devices T3 and T4, this latch is designed such that T3 and T4 have a higher impedance than T1 and T2. The input to this latch is in the form of two out-of-phase pulses A and B applied to the gates of load transistors T1 and T2, and having an up level equal to +V. Transistors T1 and T2 are powering devices for generating output signals at nodes A1 and B1. The inverse ratioing of the load and active transistors enables the latch to set into any state, dictated by the complement inputs at A and B independent of the previous state. The low-impedance feature of transistors T1 and T2 facilitates the driving of load capacitances CLA and CLB.

Fig. 2 is a waveform diagram describing the operation of the circuit. Initially, the signal at node A is up and the signal at node B is down. Node A1 is at one threshold voltage level below +V and node B1 is at ground. Device T4 is on and T3 is off. At some time node A switches to ground and node B rises to +V. Node B1 will start to rise. As its potential crosses the threshold voltage of tra...