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High Density/Performance Ratioless Dynamic Logic

IP.com Disclosure Number: IPCOM000079746D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Cordaro, W: AUTHOR [+3]

Abstract

Dynamic logic circuits are described which perform the AND function and the OR function, respectively. In the OR circuit of Fig. 1, logic input signals are applied to the gates A and B of field-effect transistors (FETs) Q3 and Q4. A pulsed phase signal is applied to the phase line B. During the time that the phase line Phi is at its high potential (assuming that N channel FETs are used), nodes X and Z are charged to the high potential through load FETs Q1 and Q2. When the phase line Phi falls to its low potential, node X is discharged through Q3 or Q4 if either or both of the input nodes A or B are high. Simultaneously, Q5 turns off and node Z is left at a high potential. Alternatively, if input nodes A and B are both low, node X remains charged when the phase line B falls to its low potential.

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High Density/Performance Ratioless Dynamic Logic

Dynamic logic circuits are described which perform the AND function and the OR function, respectively. In the OR circuit of Fig. 1, logic input signals are applied to the gates A and B of field-effect transistors (FETs) Q3 and Q4. A pulsed phase signal is applied to the phase line B. During the time that the phase line Phi is at its high potential (assuming that N channel FETs are used), nodes X and Z are charged to the high potential through load FETs Q1 and Q2. When the phase line Phi falls to its low potential, node X is discharged through Q3 or Q4 if either or both of the input nodes A or B are high. Simultaneously, Q5 turns off and node Z is left at a high potential. Alternatively, if input nodes A and B are both low, node X remains charged when the phase line B falls to its low potential. Q5 remains turned on and the output node Z is discharged to the low potential.

In the AND circuit of Fig. 2, during the time that the phase line Phi is at its high potential, nodes X, Y and Z are charged to the high potential through load devices Q1, Q2 and Q3. When the phase line falls to its low potential, nodes X and Y are discharged through devices Q4 and Q7 if input nodes A and B are high. Output node Z remains at a high potential due to the nonconduction of Q5 and Q6. Alternatively, if either input node A or input node B is low, node X or node Y, respectively, remains charged when the phase line falls to its low potent...