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Browse Prior Art Database

Two Way Exclusive "OR" Using Complementary FETs

IP.com Disclosure Number: IPCOM000079747D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Bennett, SP: AUTHOR

Abstract

The complementary field-effect transistor (FET) exclusive OR circuit shown in the drawing utilizes relatively few devices, is completely DC testable, (although an AC test may be necessary to insure N3 conducts), and dissipates minimum standby power. The exclusive OR function and the NOT thereof are readily available at respective output terminals X and Y.

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Two Way Exclusive "OR" Using Complementary FETs

The complementary field-effect transistor (FET) exclusive OR circuit shown in the drawing utilizes relatively few devices, is completely DC testable, (although an AC test may be necessary to insure N3 conducts), and dissipates minimum standby power. The exclusive OR function and the NOT thereof are readily available at respective output terminals X and Y.

The seven FETs are designated P or N in accordance With their channel conductivity types. In the event that input A is at ground (0) and input B is at the +V supply (1), FETs P2 and N4 conduct and output Y is a 0. With FET N2 off, circuit point X rises sufficiently in potential through conducting FET P2, to turn on FET N4 and prevent the output Y from rising appreciably above ground 0. In the event that input A is a 1 and input B is a 0, FETs P1 and N4 conduct in an analogous manner to provide a 0 at output Y and a 1 at point X.

When both inputs A and B are 1, FETs Nl, N2, P3 and N3 conduct.

In this case, circuit point X is prevented from rising in potential due to the simultaneous conduction of FETs N1, N2 and N3. Output Y rises to a 1 through conducting P3. Lastly, when inputs A and B are both 0, FETs P1, P2, P3 and N3 conduct producing a 1 at the output terminal Y and a 0 at circuit point X. The discharging of circuit point X, when necessary, is facilitated by FET N3 which conducts when the output terminal is above the threshold voltage of FET N3.

The above is s...