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High Density/High Performance Two Phase Dynamic Shift Register Cell

IP.com Disclosure Number: IPCOM000079751D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Cordaro, W: AUTHOR [+3]

Abstract

The shift register cell comprises a half-cell powered by phase 1 and a half-cell powered by phase 2 connected in tandem. Each half-cell comprises four field-effect transistors (FETs).

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High Density/High Performance Two Phase Dynamic Shift Register Cell

The shift register cell comprises a half-cell powered by phase 1 and a half- cell powered by phase 2 connected in tandem. Each half-cell comprises four field-effect transistors (FETs).

A logical "0" is transferred through the cell in the following manner. Referring to the figure, it is assumed initially that node A is at V(cc). If the data at the input node IN is a logical 0 (V(cc)) and P channel FETs are used, then the channels of FETs Q3 and Q4 are not formed. When phase 1 goes from V(cc) to V(gg), both nodes A and B are charged to V(gg)-V(t) through load devices Q1 and Q2. Node C is discharged through conducting FET T3. When phase 1 returns to V(cc), node B is discharged to V(cc) through conducting FET Q4. Inasmuch as the input is at V(cc), FET Q3 is off and the charge of node A remains trapped maintaining FET Q4 on. Nodes B and C are conditioned to transfer the logical 0 to the output node in the same manner during phase 2, whereby a logical 0 at the input of the cell is transferred to its output and stored there.

A logical "1" is transferred through the cell in the following manner. When the data at the input IN is a logical 1 (V(gg)-V(t)), the channel of FET Q3 is formed while node A is at V(cc) and the channel of FET Q4 is not formed. During the transition of phase 1 from V(cc) to V(gg), the input node is bootstrapped via the channel capacitance of Q3 causing node IN to charge to approxima...