Browse Prior Art Database

Parallel Series Decoder

IP.com Disclosure Number: IPCOM000079756D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Brickman, NF: AUTHOR [+6]

Abstract

In a conventional decoder both true and complement input lines must be supplied. The present decoder circuit requires only true inputs. In integrated circuit form, this provides improved reliability and smaller size. Series-parallel decoders also have this advantage, but require excessive power dissipation and provide inadequate performance levels. The present circuit solves these problems and the driver section uniquely inverts the output of the decoder to a positive going pulse, when the decoder is selected.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 72% of the total text.

Page 1 of 2

Parallel Series Decoder

In a conventional decoder both true and complement input lines must be supplied. The present decoder circuit requires only true inputs. In integrated circuit form, this provides improved reliability and smaller size. Series-parallel decoders also have this advantage, but require excessive power dissipation and provide inadequate performance levels. The present circuit solves these problems and the driver section uniquely inverts the output of the decoder to a positive going pulse, when the decoder is selected.

Fig. 1 shows a decoder stage with four inputs S1, S2, S3, S4. For this number of inputs there would be five distinct circuits (i.e. 0 parallel-4 series devices; 1 parallel-3 series; 2 parallel-2 series (shown); 3 parallel-1 series; 4 parallel-0 series). Note the last circuit would have to have minor modifications, but 15 of the 16 decoders would be constructed by changing the inputs to the first four circuits.

The operation of the circuit shown in Fig. 1 is as follows: The pulse R restores node A to one threshold below V(H). At the same time, the IG pulse charges node B to two thresholds below V(H). The output at this time is held at ground. After the restore pulse, the input signals arrive at S1, S2, S3, S4 and the decode is performed. In the case shown, node A can only go to ground potential if S1 and S2 are 0's and S3 and S4 are 1's. In all other cases, node A either remains at one threshold below ground or at a high voltage, dete...