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Browse Prior Art Database

Silicon On Sapphire On Silicon Integrated Circuit Structure

IP.com Disclosure Number: IPCOM000079760D
Original Publication Date: 1973-Aug-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 91K

Publishing Venue

IBM

Related People

Abbas, SA: AUTHOR [+3]

Abstract

Two processes are described for making a monolithic structure, combining the advantages of bipolar devices formed on silicon and complementary field-effect transistor (FET) devices formed on sapphire on silicon, one process producing polysilicon self-aligned gate FETs and the other process yielding metal gate FETs with fewer process steps.

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Silicon On Sapphire On Silicon Integrated Circuit Structure

Two processes are described for making a monolithic structure, combining the advantages of bipolar devices formed on silicon and complementary field- effect transistor (FET) devices formed on sapphire on silicon, one process producing polysilicon self-aligned gate FETs and the other process yielding metal gate FETs with fewer process steps.

In both processes, a P silicon substrate is provided on which a 1.5 to 2.0 micrometer sapphire epitaxial layer is grown. A 0.5 to 0.75 micrometer thick pyrolytic oxide layer is deposited on the sapphire. Then, in the polysilicon self- aligned gate FET process, bipolar transistor subcollector windows are opened (n the pyro oxide and underlying sapphire. An N+ re&ion is diffused into the substrate and then N epitaxial silicon is deposited to a thickness of about 1 - 1.5 micrometers. The resulting polysilicon on the pyro oxide and the pyro oxide itself are removed by etching.

A second epitaxial layer of N type silicon is grown to a thickness of about
0.75 micrometer. Pyrolytic oxide is deposited on the second silicon epi. Dielectric isolation areas are opened in the pyro oxide and about 50% of the underlying epitaxial silicon is etched out. The remaining epitaxial silicon in the dielectric isolation window areas is reoxidized, until the oxide reaches the underlying sapphire.

The N-channel FET device areas are opened through the pyrolytic oxide. A partial ion-implantation mask, e.g., silicon nitride of predetermined thickness, is deposited in the N-channel device areas. The base regions of the bipolar transistors are opened through the pyrolytic oxide. Boron is ion-implanted to achieve a desired base profile in the bipolar base area, and a substantially lesser dose in the N-channel FET region for threshhold voltage control purposes. The remaining pyro oxide is removed, the underlying silicon is reoxidized and successive layers of silicon nitride and pyrolytic oxide are deposited thereon.

The bipolar transistor regions are opened through the pyrolytic oxide, silicon nitride and reoxidized layer. The pyrolytic oxide is removed and a P epitaxial silicon layer is deposited, to form the base of the bipolar transistors and the polysilicon dates in the FET areas. The polysilicon is covered by oxide. The FET gates are defined and protected by reoxidation and lat...