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Browse Prior Art Database

Simultaneously Forming Memory and Support Circuits Using FETs

IP.com Disclosure Number: IPCOM000079765D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR

Abstract

Arrays of metal - silicon nitride - silicon dioxide - silicon semiconductor (MNOS) devices have been proposed for data storage. Efficient operation requires that the portion of the nitride layer facing the oxide layer be leaky for data writing, and that the opposite portion of the nitride layer have high resistivity for data retention. The following process forms such MNOS devices simultaneously with MOS support circuit devices having no nitride layers therein.

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Simultaneously Forming Memory and Support Circuits Using FETs

Arrays of metal - silicon nitride - silicon dioxide - silicon semiconductor (MNOS) devices have been proposed for data storage. Efficient operation requires that the portion of the nitride layer facing the oxide layer be leaky for data writing, and that the opposite portion of the nitride layer have high resistivity for data retention. The following process forms such MNOS devices simultaneously with MOS support circuit devices having no nitride layers therein.

N epitaxial layer 1 of Fig. 1 is grown on P substrate 2. p+ isolation diffusion 3 is made through epi layer 1. The epitaxial layer is oxidized and source and drain windows are opened for the support circuit and the memory array field-effect transistors (FETs).

In Fig. 2, P+ diffusions 4 and 5 are made for the support FET, while P+ diffusions 6 and 7 are made for the memory FET and the structure is reoxidized.

The gate region for each memory FET is opened and thin oxide layer 8 and thicker silicon nitride layer 9 are formed. The silicon nitride is removed everywhere except in the gate region of each memory FET, as shown in Fig. 3. The support FET gate region is opened and the entire structure is oxidized, forming the gate dielectric of each support FET and simultaneously oxygen annealing the silicon nitride in the gate area of each memory FET. The temperature and time parameters of the oxidation step are adjusted to yield an oxynitride layer 10 o...