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Passivated Refractory Gate Field Effect Transistor

IP.com Disclosure Number: IPCOM000079776D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Gardiner, JR: AUTHOR [+2]

Abstract

This field-effect transistor has structure that eliminates the problem of moisture attack to the refractory gate material, which refractory gate material is necessary in using self-aligning gate process.

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Passivated Refractory Gate Field Effect Transistor

This field-effect transistor has structure that eliminates the problem of moisture attack to the refractory gate material, which refractory gate material is necessary in using self-aligning gate process.

In this process, an SiO(2) layer 12 is deposited on silicon semiconductor body 10 by conventional techniques. An opening 14 is made in layer 12 that overlies the gate, source, and drain regions. A thin gate dielectric layer 16 is deposited or grown in opening 14, preferably by thermally oxidizing the silicon body 10 and the refractory gate 18 formed by blanket deposition of a metal layer and subtractive etching, using conventional photolithographic techniques.

As shown in Fig. 2, the thin dielectric layer 16 is removed from the source and drain openings by dip etching. As indicated in Fig. 3, a doped dielectric layer 20 is deposited on the surface of the device. Layer 20 can be produced by conventional chemical vapor deposition techniques and can be phosphosilicate glass or borosilicate glass. A heating step causes the semiconductor impurities in layer 20 to diffuse into the surface of body 10 forming source region 22 and drain region 24.

As indicated in Fig. 4, a blanket layer 26 of Si(3)N(4) is then deposited by chemical vapor deposition techniques or sputtering and openings for the source, drain and gate regions made, as indicated in Fig. 5. Metal contacts for the source, drain and gate region are then formed...