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Refresh System for Dynamic Hierarchy Storages

IP.com Disclosure Number: IPCOM000079781D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Barsuhn, HE: AUTHOR [+2]

Abstract

In storages with dynamic monolithic storage cells, such as backing storages, information is stored in integrated capacities by an electric charge. This results in unavoidable leakage currents, which call for the charge to be refreshed after a certain period of time.

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Refresh System for Dynamic Hierarchy Storages

In storages with dynamic monolithic storage cells, such as backing storages, information is stored in integrated capacities by an electric charge. This results in unavoidable leakage currents, which call for the charge to be refreshed after a certain period of time.

In very large storages the ratio of the read cycles and the subsequent refresh cycles becomes increasingly unfavorable, so that the mean access time deteriorates. For this reason the dynamic storage is sub-divided into two parts, one of the two parts being addressed by the low-order bit and a refresh cycle being executed on the other. Addressing by the low-order address bit is possible, because the data blocks, arranged in a consecutive address-sequence, are transferred between the backing storage and the buffer.

A control logic ensures that the various refresh cycles sequentially affect all addresses of the storage matrix, irrespective of whether the storage has been addressed or is on standby. This subdivision of the storage and the described addressing permit the address and refresh cycles to be performed parallel to each other, so that an addition of the two cycles resulting in essentially reduced access times is prevented.

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