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Dynamic FET Shift Register Cell with DC Stability

IP.com Disclosure Number: IPCOM000079796D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Nosowicz, EJ: AUTHOR [+2]

Abstract

This field-effect transistor (FET) shift register cell provides a 3-phase dynamic shift register position function with DC stability. Low-power dissipation and small cell size result, which are two features sacrificed in most DC stable cells.

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Dynamic FET Shift Register Cell with DC Stability

This field-effect transistor (FET) shift register cell provides a 3-phase dynamic shift register position function with DC stability. Low-power dissipation and small cell size result, which are two features sacrificed in most DC stable cells.

Data can be a logical "1" or "0". The operation for both cases is similar. For purposes of illustration, assume the data is a 1. The static enable line ST is down for the shift cycle. With line ST down, T8, T4 and T5 are essentially disconnected.

Clock phi 1 rises to a high level, gating the data signal to the gate of T3 where it is capacitively stored when phi 1 comes down.

Clock phi 2 rises and unconditionally charges the line C (complement) When phi 2 falls, line C will remain charged or discharged depending upon the state of the gate of T3. In the present case, the gate is a 1 and line C discharges through T3.

Clock phi 3 rises and unconditionally charges line T (true) through T6. When phi 3 falls, line T remains charged or discharged depending upon the state of the gate of T7. In the present case, it remains unchanged and data has been transferred to T and its complement to C.

To transform the cell to a DC stable state, line ST is brought up. T4, T4 and T8 are turned on forming a stable DC latch.

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