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Circuit for the Complete Check of a Data Processing System

IP.com Disclosure Number: IPCOM000079814D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Geng, HR: AUTHOR [+4]

Abstract

With the increasing integration of circuits it has become desirable to check system functions not only in the data flow by parity bits, but to include in the checking also the control functions. This is for instance possible by means of known circuits of the majority principle. There, to give an example, three systems execute the same function in parallel, compare the results, and use the result of the majority of these systems as the probably correct result. This kind of checking, however, requires quite complex circuitry and above all a complex system of connecting lines.

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Circuit for the Complete Check of a Data Processing System

With the increasing integration of circuits it has become desirable to check system functions not only in the data flow by parity bits, but to include in the checking also the control functions. This is for instance possible by means of known circuits of the majority principle. There, to give an example, three systems execute the same function in parallel, compare the results, and use the result of the majority of these systems as the probably correct result. This kind of checking, however, requires quite complex circuitry and above all a complex system of connecting lines.

In particular the number of connecting lines to the associated majority circuit, the number having been considerably increased in accordance with the number of systems operating in parallel, presents highly critical problems in connection with the large-scale integrated (LSI) circuits; and in that field especially at a "full wafer approach", where a wafer is no longer cut into individual "chips".

In order to achieve a high-wafer yield, modern technology, on the other hand, assembles circuits (e.g. 1,000) to completely wired islands. Of each type of island required in the system there consequently exist several on one wafer. After a functional test the faultless islands are wired to each other with discrete connections, their outputs, however, being controllably switchable. A faulty island can thus be switched off.

It is the object of the present description to utilize the circuit redundance (for manufacturing reasons) for the checking. For the checking of the functions in the system, the circuit according to the figure is suggested.

All switchable outputs of the islands are directly interconnected at point P for the equivalent signals, so that there is the same information at returning lines R1, R2. The thus returned information is compared with the corresponding output data of the respective logic in the i...