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Search and FIFO Replacement Hardware Mechanism for a Buffer Concept

IP.com Disclosure Number: IPCOM000079828D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Gomez, JA: AUTHOR

Abstract

This is a minimized hardware mechanism which implements search and first in-first out (FIFO) replacement functions, by using one commonly-shared ring counter and a set of three highly interrelated registers.

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Search and FIFO Replacement Hardware Mechanism for a Buffer Concept

This is a minimized hardware mechanism which implements search and first in-first out (FIFO) replacement functions, by using one commonly-shared ring counter and a set of three highly interrelated registers.

The counter, CTR, the pointer, PTR and FIFO each comprise three AND/ OR invert latches. In the diagram, the FIFO 14 and CTR 10 are designated as latches while the PTR 12 is referred to as triggers. Free-running clocking pulses, LC, are sent to CTR 10 and FIFO 14 at half a cycle difference from TC, the free- running clocking pulse sent to PTR 12. The actual ring counting function is gated by gate counter, GC, and gate, FIFO, GF, allowing this mechanism to behave as a ring counter for CTR 10 or for FIFO 14, respectively. The absence of both GC and GF provides a reset condition to PTR 12. Hold FIFO, HF, is a control signal which allows FIFO 14 to "remember" a specific prereplacement value. Hold pointer, HP, is a control signal which allows PTR 12 to maintain specific replacement or search values, which are supplied to a word select decoder 18 in a grey code sequence. Both HF and HP represent clock degating functions to LC, at FIFO only, and to TC, respectively.

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