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Browse Prior Art Database

Address Reconfiguration for Large Scale Integrated Memory Yield Enhancement

IP.com Disclosure Number: IPCOM000079870D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Bossen, DC: AUTHOR [+3]

Abstract

This scheme permits the use of single bad bit memory chips with the loss of only one bit position of the chip.

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Address Reconfiguration for Large Scale Integrated Memory Yield Enhancement

This scheme permits the use of single bad bit memory chips with the loss of only one bit position of the chip.

The chips are arranged in a bit per basic operating memory (BOM) configuration, each chip containing the same bit position of a number of different words. On each chip there is an exclusive OR circuit 10 for each input to the decoder 12 for the chip. One input to each of these exclusive OR's 10 is a digit from the bit select signal 14, while the other input is a position in a control register 16 contained on the chip. The control register 16 stores the address of the bad bit, in the illustrated case 11110000.

When the data in this had bit is requested by the bit selection digits 14, bit 00000000 is accessed in place of the bad bit. Thus, all bad bits are mapped into the 00000000 position on all the chips in the bit per BOM configuration. To accommodate the data to be stored in the 00000000 position of all the different chips, an all good chip is addressed to the array. When the 00000000 position is then requested, the all good chip is accessed and all the bits for that chip are read out.

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