Browse Prior Art Database

Block Interleaving in Multilevel Memory Systems

IP.com Disclosure Number: IPCOM000079871D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Annunziata, EJ: AUTHOR [+2]

Abstract

This data organization scheme is effective in multilevel memory systems. This description deals with another form of address interleaving where the unit of data delivered to the system is still a line: however, the double-word addresses are consecutive for a block of data (say 256 bytes) within a basic system memory (BSM), with consecutive blocks located in consecutive BSM's. This arrangement is especially suited for a storage system where another level of storage hierarchy is employed.

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Block Interleaving in Multilevel Memory Systems

This data organization scheme is effective in multilevel memory systems. This description deals with another form of address interleaving where the unit of data delivered to the system is still a line: however, the double-word addresses are consecutive for a block of data (say 256 bytes) within a basic system memory (BSM), with consecutive blocks located in consecutive BSM's. This arrangement is especially suited for a storage system where another level of storage hierarchy is employed.

Assuming a two level of hierarchy BSM (L2 and L3) below the cashe level (L1) and assuming the unit of transfer between L2 and L3 to be 256 bytes within a single BSM, then ideally the size of contiguous block addresses selected between BSM's could be 256 bytes. With this arrangement, the storage system would he better utilized, especially in a multiprocessor environment, because this concept could give a type of random activity which is desirable for a storage system where multiple BSM's are used. In addition, the paging activity between L2 and L3 could be controlled in increments of the BSM block size.

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