Browse Prior Art Database

Bootstrap Capacitor Control

IP.com Disclosure Number: IPCOM000079884D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Cox, DT: AUTHOR [+3]

Abstract

A controlled charge is stored into bootstrap capacitor C1 only immediately prior to the time when transistor 37 will be turned on. In operation, nodes 20 and 22 of the latch comprising cross-compiled field-effect transistors (FETs) 11, 13, load transistors 15, 17, gate transistors 23, 25, and switching transistors 19, 21, are both held at a down level by up level signals at bit-sense line B and bit-sense line A. Node 22 being at a down level causes FET 31 to remain off, allowing FET 27 to hold FET 39 on. Likewise, FET 33 will be held on because, as previously recited, bit-sense line A is at an up level and node 22 is at a down level. Both nodes 34 and 38 will also be at a down level.

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Bootstrap Capacitor Control

A controlled charge is stored into bootstrap capacitor C1 only immediately prior to the time when transistor 37 will be turned on. In operation, nodes 20 and 22 of the latch comprising cross-compiled field-effect transistors (FETs) 11, 13, load transistors 15, 17, gate transistors 23, 25, and switching transistors 19, 21, are both held at a down level by up level signals at bit-sense line B and bit-sense line A. Node 22 being at a down level causes FET 31 to remain off, allowing FET 27 to hold FET 39 on. Likewise, FET 33 will be held on because, as previously recited, bit-sense line A is at an up level and node 22 is at a down level. Both nodes 34 and 38 will also be at a down level.

The only time transistor 37 will turn on is if bit-sense line A goes to a down level. When this occurs, FET 33 immediately turns off, but FET 39 cannot turn off until node 22 has risen to a sufficient level to cause FET 31 to begin conducting. During this interval of time, FET 35 is charging capacitor C1 through FET 39 in preparation for charging node 38 to a full up level. By the time FET 39 has turned off, capacitor C1 has adequate charge to hold the gate of FET 37 sufficiently above its source, so that it is capable of providing substantial up level drive currents at a full up level voltage.

This circuit improves worst-case delay, while at the same time reducing worst-case power dissipation. Nominal and best-case performance is also less sensitive, beca...