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True Complement Generator Circuit with Schottky Barrier Diodes

IP.com Disclosure Number: IPCOM000079889D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Park, SJ: AUTHOR

Abstract

In response to an input signal at input node V(in), the circuit provides a true and a complement output signal at nodes c and c. When input node V(in) is at an up level, transistors T1 and T3 conduct and generate a down level at output node c. Transistor T4 is nonconducting and, therefore, output node c is at an up level. Conversely, when the input is at down level, output node c is up level and output node c is at a down level.

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True Complement Generator Circuit with Schottky Barrier Diodes

In response to an input signal at input node V(in), the circuit provides a true and a complement output signal at nodes c and c. When input node V(in) is at an up level, transistors T1 and T3 conduct and generate a down level at output node c. Transistor T4 is nonconducting and, therefore, output node c is at an up level. Conversely, when the input is at down level, output node c is up level and output node c is at a down level.

The circuit provides a maximum noise tolerance for the input signal by the utilization of Schottky diodes D5, D6, D7, D8, D9, D10.

The plurality of associated Schottky barrier diodes D1, D2, D3, D4 clamp the base to collector junction of their respective saturated transistors. Large saturation time delays are avoided or kept to a minimum, since transistors T1, T3, and T7 are maintained at minimum saturation biasing levels.

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