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Recessed Oxide Insulation for Improving Interlevel Metallurgy Densities

IP.com Disclosure Number: IPCOM000079892D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Dorler, JA: AUTHOR [+2]

Abstract

Higher integrated circuit densities can be realized through improved chip wiring techniques, such as multilevel metallurgy. This requires methods of interconnection between levels, normally referred to as interlevel vias. Due to processing and mask tolerances during the etching of the via holes, silicon is sometimes exposed causing undesirable shorts. This short is due to a relatively thin oxide which remains on the etched silicon. To avoid this problem in the past, metal lines 10 and 12 are enlarged around the via holes 14 and 16 located on the substrate 18, Fig. 1. However the enlarged areas reduce obtainable densities.

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Recessed Oxide Insulation for Improving Interlevel Metallurgy Densities

Higher integrated circuit densities can be realized through improved chip wiring techniques, such as multilevel metallurgy. This requires methods of interconnection between levels, normally referred to as interlevel vias. Due to processing and mask tolerances during the etching of the via holes, silicon is sometimes exposed causing undesirable shorts. This short is due to a relatively thin oxide which remains on the etched silicon. To avoid this problem in the past, metal lines 10 and 12 are enlarged around the via holes 14 and 16 located on the substrate 18, Fig. 1. However the enlarged areas reduce obtainable densities.

To increase metal line densities, as depicted in Fig. 2, wiring channels are filled with recessed oxide insulation. The vias are dropped in this recessed oxide insulation channel. Since the recessed oxide insulation is relatively thick, approximately 10,000 angstroms, the probability of etching through to the silicon is minimal. Consequently, with this additional safety factor, there is less danger of the silicon being exposed and thus the overlap of the metal in the areas 20 of via holes 22 and 24 is unnecessary. This results in closer spacing of the metal lines 26 and 28 located on the semiconductor substrate 30, and thus improved densities are realized.

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