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High Density Schottky Diode Array Design

IP.com Disclosure Number: IPCOM000079895D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Dorler, J: AUTHOR [+3]

Abstract

The figures illustrate the horizontal (b) and vertical (c) design of the Schottky array segment shown on (a). The design technique represents a unique way of designing, in particular, high-density Schottky arrays. It incorporates the use of an N+ buried layer and a second level metal conductor, commoned by diffusions and interlay vias, to reduce the prohibitive cathode resistance inherent in common cathode Schottky barrier diode (SBD) configurations. The cathode resistance associated with any diode position with an array segment is, R(n) = n(k+1-n) over k+1 ra where R(n) = cathode resistance of diode n k = total # of diodes between via contacts n = diode position.

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High Density Schottky Diode Array Design

The figures illustrate the horizontal (b) and vertical (c) design of the Schottky array segment shown on (a). The design technique represents a unique way of designing, in particular, high-density Schottky arrays. It incorporates the use of an N+ buried layer and a second level metal conductor, commoned by diffusions and interlay vias, to reduce the prohibitive cathode resistance inherent in common cathode Schottky barrier diode (SBD) configurations. The cathode resistance associated with any diode position with an array segment is, R(n) = n(k+1-n) over k+1 ra

where R(n) = cathode resistance

of diode n

k = total # of diodes

between via contacts

n = diode position.

Thus the resistance, R(n), can be tailored to any value required for the circuit by appropriate placements of via contacts, and is not a strict function of the number of diodes in the array.

A semiconductor substrate 1 has formed adjacent its upper surface, an N+ diffused buried layer 2 above which is formed an N type epitaxial layer 3. The latter is covered by a silicon dioxide-nitride layer 4 having contact holes, through which extends the first level of metallization 5. Superimposed on the latter is a silicon dioxide layer 6 on the upper surface, on which is deposited a second layer of metallization 7.

The advantage of the described structure, is the parallel connection of subcollector 2 and second level metallization 7 to reduce the resistance of the diode el...