Browse Prior Art Database

Liquid Crystal Display Driver Using Complementary Metal Oxide Silicon Transistors

IP.com Disclosure Number: IPCOM000079901D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Ainsworth, RA: AUTHOR

Abstract

Electronic watches utilizing liquid crystal display elements, require the use of voltages in the region of 15 volts to turn on the display. The semiconductor chips used in the electronic circuitry of the watch are preferably fabricated in complementary metal-oxide semiconductor (CMOS) technology, which is driven by 3 volts. This requires a circuit to interface the 3 volt logic level with the 15 volt liquid crystal display.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Liquid Crystal Display Driver Using Complementary Metal Oxide Silicon Transistors

Electronic watches utilizing liquid crystal display elements, require the use of voltages in the region of 15 volts to turn on the display. The semiconductor chips used in the electronic circuitry of the watch are preferably fabricated in complementary metal-oxide semiconductor (CMOS) technology, which is driven by 3 volts. This requires a circuit to interface the 3 volt logic level with the 15 volt liquid crystal display.

In the figure, devices P1 and N2 comprise an inverter; device P3 is for isolating node A from node B; devices P4 and P5 form a 2-way AND gate; devices N7, P10, N13 and P14 are field-effect transistor (FET) diodes; device P12 is used to inject a small DC current into node H, to maintain node G negative enough to hold off device N9 when the output is at ground. BIAS input is shared by many similar circuits and is returned to ground, either through a FET P- channel device with a gate having a width-to-length ratio of much less than 1.0 or through a resistor.

In operation, with the data IN line at -3V, node A is at ground holding devices P4 and P12 OFF and device P3 on.

Node E charges to ground through P1 and P3; in turn devices p6 and N9 are held off and on, respectively, because node G is at a voltage below ground which is equivalent to the threshold drops across devices P14 and N13. The output line is held at -15V.

The only DC power dissipated is that required to maintain node E charged at ground. Device N8 is designed to have a gate width-to-length (W/...