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Selective Planar GaP/Si Deposition Process with Self Isolated Light Emitting Diodes

IP.com Disclosure Number: IPCOM000079903D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Broadie, RW: AUTHOR [+2]

Abstract

With the use of standard silicon hole etching, thermal oxidation and photoresist processing, a configuration as shown in Fig. 1 is realized having an oxide layer 1 and an etched hole 2 in the silicon substrate 3.

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Selective Planar GaP/Si Deposition Process with Self Isolated Light Emitting Diodes

With the use of standard silicon hole etching, thermal oxidation and photoresist processing, a configuration as shown in Fig. 1 is realized having an oxide layer 1 and an etched hole 2 in the silicon substrate 3.

A pyrolytic (or other nonselective) GaP layer is deposited over the whole structure. The polycrystalline GaP over the SiO(2) layer is removed by etching with HF, leaving only epitaxial GaP in the bottom of the hole. Gap is then deposited by a disproportionation process which selectively grows only on GaP. The result is shown in Fig. 2. The gap 4 between the Si substrate 3 and the GaP 5 is filled in with a "paint-on SiO(2)" to achieve a planar surface.

This method exhibits the following advantages. The GaP-Si material contact is minimized to keep stress problems to a minimum, planar surface is achieved to aid in GaP light-emitting diode - Si device processing, wafer bowing is eliminated, optical isolation between adjacent diodes is realized, and the process sequence permits controlled selective growth.

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