Browse Prior Art Database

Cell for Variable Length Buffer Shift Register

IP.com Disclosure Number: IPCOM000079920D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Vautier, R: AUTHOR

Abstract

Shown is a cell which is an elementary part of a buffer shift register that permits interconnection of systems working at different instantaneous bit rates.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 58% of the total text.

Page 1 of 2

Cell for Variable Length Buffer Shift Register

Shown is a cell which is an elementary part of a buffer shift register that permits interconnection of systems working at different instantaneous bit rates.

The register comprises N similar cells. To be queued in the output data stream, an incoming bit must be written in the right position taking into account the location of the last introduced bit.

In order to locate the last introduced data bit, data bits X are preceded by a "1" flag bit and the positions at the left of the flag contain "0" bits. Assuming that N equals ten, the hits contained in the cells comprising the register are for example: 0 0 0 1 X X X X X X.

Each time a data bit is shifted out of the rightmost cell of the register, a 0 bit is introduced in the leftmost cell.

When a data bit is to be introduced in the register it must take the flag place and the flag must be left shifted. If the data bit is a 1 bit, the cell which was occupied by the flag is not changed. If the data bit is a 0 bit, the cell which was occupied by the flag is reset to 0.

A cell capable of performing these operations comprises: a latch FF having a set input circuit S and a reset input circuit R, logic AND gates A1, A2, A3, and control lines. Circuit S comprises two AND gates A4 and A5 and an OR gate 01. Circuit R comprises two AND gates A6 and A7 and an OR gate 02.

When a read operation is to be performed, the READ line is set to an UP level. Depending upon the status of the pr...