Browse Prior Art Database

Channel To Channel Adapter

IP.com Disclosure Number: IPCOM000079923D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Douglas, GL: AUTHOR

Abstract

This channel-to-channel adapter allows the connection of two otherwise incompatible channels. In the figure, channel 10 of processor 1 includes separate data input and data output lines, with address information to input-output (I/O) devices being conveyed on the data output line. Channel 20 conveys input and output data to I/O devices 2, 3, 4, ... N on a common set of lines; however, separate address lines are included on channel 20. Further, interrupt lines are separated from the data and address lines on channel 20, while interrupt information is conveyed along the data input lines of channel 10 to processor 1.

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Channel To Channel Adapter

This channel-to-channel adapter allows the connection of two otherwise incompatible channels. In the figure, channel 10 of processor 1 includes separate data input and data output lines, with address information to input- output (I/O) devices being conveyed on the data output line. Channel 20 conveys input and output data to I/O devices 2, 3, 4, ... N on a common set of lines; however, separate address lines are included on channel 20. Further, interrupt lines are separated from the data and address lines on channel 20, while interrupt information is conveyed along the data input lines of channel 10 to processor 1.

Channel-to-channel adapter 30 resolves the above incompatibilities between channel 10 and channel 20. Data and address information from processor 1 to the I/O devices is conveyed along data output lines 31 of channel 10. The data and address information is separated and temporarily stored in data register 36 and address register 37, respectively, through the selective gating of the data and address information through AND gates 38 and 39, which are selectively enabled by timing generator 40. Data and address information are therefore, separated, after which data is selectively gated out of register 36 through AND gate 41 to data lines 33 of channel 20, and address information is selectively gated out of register 37 through AND gate 42 to address lines 34 of channel 20. Lines 33 denote the common set of data input and output l...