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Cost Optimized Walking Counter Synchronization

IP.com Disclosure Number: IPCOM000079935D
Original Publication Date: 1973-Sep-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Douglas, GL: AUTHOR

Abstract

Fig. 1 is a map which depicts all of the possible states of a six-stage walking counter (N=6). The states of the regular mode are shown circled without subscripts. The subscripted numbers indicate the various states of all the crazy modes, where the number is the state, and the subscript is the crazy mode. There are five possible crazy modes.

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Cost Optimized Walking Counter Synchronization

Fig. 1 is a map which depicts all of the possible states of a six-stage walking counter (N=6). The states of the regular mode are shown circled without subscripts. The subscripted numbers indicate the various states of all the crazy modes, where the number is the state, and the subscript is the crazy mode. There are five possible crazy modes.

In Fig. 5, which is like the one described in IBM Technical Disclosure Bulletin, Vol. 15, No. 6, November, 1972, pages 1848 and 1849, when the counter is running in the regular mode, at sample time AB, C and D and E and F are all true, and NAND gate 1 provides an inhibit on NAND gate 2, so that only NAND gate 3 controls the setting and resetting of the B stage of the counter. When the counter is running in any of the crazy modes, at sample time AB, either C or D or E or F is false (perhaps more than one is false) and NAND gate 1 inhibit is released, allowing NAND gate 2 to keep flip-flop B turned on (true state) until such time as the NAND gate 1 provides an inhibit to NAND gate 2, which by definition is a state in the regular mode.

In Fig. 2, B always sets when A comes true (on the next clock cycle), but resets only when A has reset and all the other flip-flops (C through F) are turned on, which is a state in the regular mode. Thus, the same function as provided by the counter stage of Fig. 5 is performed in a simpler manner by the counter stage of Fig. 2.

Fig. 2 shows an implementation which keeps flip-flop B from resetting till all the higher ordered flip-flops (C through F) are turned on. The cost of this implemen...