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Browse Prior Art Database

Hierarchical Storage Chip

IP.com Disclosure Number: IPCOM000079939D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Beausoleil, WF: AUTHOR [+4]

Abstract

The drawing shows a schematic representation of a common configuration for prior art storage devices constructed on monolithic circuit chips with the addition of a buffer. The chip is utilized to construct a memory system having a plurality of modules, each with a plurality of chips.

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Hierarchical Storage Chip

The drawing shows a schematic representation of a common configuration for prior art storage devices constructed on monolithic circuit chips with the addition of a buffer. The chip is utilized to construct a memory system having a plurality of modules, each with a plurality of chips.

Each of the monolithic storage chips would contain a matrix 1 of binary data storage cells, a binary data storage cell being located at each of the intersections
2. Also included on the monolithic storage chip would be terminals for receiving binary address bits A0-A6. By a word decoder 3 and word drivers 4, address bits A0-A3 would be decoded to energize one of sixteen word drivers to thereby cause the data in a particular one of the horizontal rows of data cells to produce signals representing binary 0's or binary 1's, on all the eight vertical lines of the matrix. Bit decoder 5 and bit drivers and sense preamp 6 will be effective in response to address bits A4-A6, to permit the binary data to be stored in, or read out from, a particular one of the eight storage cells in the row accessed by the word decoder 3.

Additional circuitry is added to the chip to provide a buffer 7 in the form of latch or trigger circuits, for the purpose of storing the information found on all of the eight vertical lines of the storage device. The access time to the array 1 is now slightly increased to the time required to latch-up the data in the selected horizontal row of storage cells 2. Access time to data within a particular storage cell of the matrix 1, is a function of the time required for the word decoder 3 to resolve the combination of address bits A0-A3.

By utilizing various known techniques, a particular one of the storage cells in the buffer 7 can be selected utilizing only three binary address bits A4-A6, the decode time of which is less than that required to decode bits A0-A3. In addition to the decoding of A0-A3, drivers must be energized, sense lines sampled...