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Orthogonal Shift Register Implementation of Interlaced Error Correction Codes

IP.com Disclosure Number: IPCOM000079973D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Ouchi, NK: AUTHOR

Abstract

Fig. 1 shows an interlaced data with a resulting interlaced error correction code (ECC) output. Fig. 2 shows the system configuration for generating the necessary ECC information for each record of interlaced data, using only one ECC generator.

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Orthogonal Shift Register Implementation of Interlaced Error Correction Codes

Fig. 1 shows an interlaced data with a resulting interlaced error correction code (ECC) output. Fig. 2 shows the system configuration for generating the necessary ECC information for each record of interlaced data, using only one ECC generator.

As input information is received, it is passed through the system by OR circuit
1. The input is also fed into ECC generator 2, for generating a partial ECC associated with the portion of the interlaced information being processed. Control storage 3 is connected to the ECC generator 2. Control storage 3 is comprised of storage registers 1, 2 and 3 as well as control circuitry. Control storage 3 further has an input indicative of the start of a record and the end of that record, as well as timing inputs associated with the interlaced information.

In operation at the start of a record, the ECC generator is cleared as is all of the storage registers 1, 2 and 3. As the first information associated with A is received, it is stored into the ECC generator 2 and a partial check word associated with data A is generated. At B time, the contents of the shift of the ECC generator 2 is shifted into storage register 3 and the contents of storage register 1 are shifted into the ECC generator. In similar manner, the contents of storage register 2 are shifted into storage register 1 and the contents of storage register 3 are shifted into storage register 2. It can...