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Random Access Memory Implementation of Interlaced Error Correction Codes

IP.com Disclosure Number: IPCOM000079974D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 5 page(s) / 111K

Publishing Venue

IBM

Related People

Ouchi, NK: AUTHOR [+2]

Abstract

A higher performance system can decode and correct (or encode and decode) consecutive messages with one set of I and T networks, if the networks and memory have sufficient band widths. This is done by interleaving decode (encode) and correction (decode) cycles. That is, while b-bits are being accumulated, the error correction code (ECC) state of the present message block can be generated, followed by the syndrome ECC state generation for the previous message. Hence, both decode (encode) and correction (decode) can proceed at the message rate. The correction will be delayed by one message time. The band width of the 1 and T networks and the memory can be increased by parallel implementation. The limit, of course, is N parallel implementations for an N-order interlaced code.

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Random Access Memory Implementation of Interlaced Error Correction Codes

A higher performance system can decode and correct (or encode and decode) consecutive messages with one set of I and T networks, if the networks and memory have sufficient band widths. This is done by interleaving decode (encode) and correction (decode) cycles. That is, while b-bits are being accumulated, the error correction code (ECC) state of the present message block can be generated, followed by the syndrome ECC state generation for the previous message. Hence, both decode (encode) and correction (decode) can proceed at the message rate. The correction will be delayed by one message time. The band width of the 1 and T networks and the memory can be increased by parallel implementation. The limit, of course, is N parallel implementations for an N-order interlaced code. Interlaced recurrent codes can also be implemented in a very similar manner, and would benefit from the cost savings.

Except for very simple short codes, the I and, especially, T exclusive OR (EOR) networks are complex and require a significant number of circuits and have limited application. On the other hand, the random-access structure is very regular and can be fabricated in high-density, low-cost LSI. It also has many other applications and benefits, from a cost standpoint, by its wide usage. This implementation takes advantage of the cost and module savings afforded by the random-access memory. It also provides a significant savings in the control logic, since it too is interlaced in its usage. The random-access array provides flexibility in the manner in which multiple bursts of messages are processed.

Fig. 1 illustrates the 1, T and random-access memory implementation. The control logic is not shown. However, the addressing counters are shown. This implementation stores the blocks in byte form in consecutive storage locations rather than in parallel. This logic permits a single encode, decode, or correction process.

Fig. 2 illustrates an implementation which allows simultaneous processing of any two encode, decode, or correction processes. The correction can be double- error correction with appropriate control logic. The processes are interleaved. That is, during a b-bit accumulation time, one cycle of each process is accomplished. Hence, a message being received can be decoded while a previous message is corrected, or a message can be encoded and transmitted while a message is received and decoded. The double-error correction process:
1) Two error pointers are associated with each code word. These are processed cyclically and may be in a similar cyclic memory structure as the syndromes. Call these two pointers.i and j. 2) The value j - i is mapped to a value k, where (I + T/j-i/) = T/-k/. 3) The value k is placed in the memory location (n, k) associated with the code word. 4) The value L - i is placed in the memory location (n, i'), where L is the full length of the code. 5) The va...