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Obtaining Improved Josephson Gate Characteristics for Use in Logic Circuits

IP.com Disclosure Number: IPCOM000079989D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Basavaiah, S: AUTHOR [+2]

Abstract

At present, rectangular in-line gates are used-to design terminated logic circuits. Fig. 1 depicts the gate current, I(g) vs. control current, I(c) characteristics of such an in-line gate, where the maximum slope obtainable is -1. This places severe restrictions on the margins obtainable in designing logic circuits.

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Obtaining Improved Josephson Gate Characteristics for Use in Logic Circuits

At present, rectangular in-line gates are used-to design terminated logic circuits. Fig. 1 depicts the gate current, I(g) vs. control current, I(c) characteristics of such an in-line gate, where the maximum slope obtainable is -1. This places severe restrictions on the margins obtainable in designing logic circuits.

An arrangement is proposed to solve the problem. It can be shown that an ideal I(g) vs. I(c) characteristic to be used in logic circuits is that shown in Fig. 2. A fairly close approximation to the characteristic shown in Fig. 2 has been demonstrated experimentally by using: 1) a single junction cross-control gate, and 2) using the Josephson current density and the gate dimensions, such that the length, L, and the width, W, of the gate are >/- 5 lambda(j), where lambda(j) is the Josephson penetration length.

Fig. 3 illustrates the proposed gate geometry while Fig. 4 shows the resulting I(g) vs. I(c) characteristics. The slopes of 3 and 3.6 that were obtained in the experiment depend on the relative dimensions of gate and control lines. These can be increased. The extent of the flatness appears to depend on the L/lambda(j) ratio which can also be altered, if desired.

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