Browse Prior Art Database

Polarity Independent Write Compensation

IP.com Disclosure Number: IPCOM000080030D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Weiss, RL: AUTHOR

Abstract

Undesirable transition phase shifts occurring during recording and reading of (for example) phase-encoded data on magnetic media are compensated for prior to recording, regardless of the transition signal polarity.

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Polarity Independent Write Compensation

Undesirable transition phase shifts occurring during recording and reading of (for example) phase-encoded data on magnetic media are compensated for prior to recording, regardless of the transition signal polarity.

Referring to Fig. 2, if positive (upward) or negative (downward) transitions move from their desired positions, recorded data may be misinterpreted. This is cured during recording by independently predicting the amount of forward shift which will occur for each transition and compensating for it, by delaying that transition an equal amount.

In Fig. 1, input data intended for recording is entered into a shift register, so that the period preceding and following each transition may be monitored by a decoder. A short period is indicated by a 1 and a long period by a 2. Thus, a transition 22 is preceded and followed by long periods. Depending upon the stored data, a different delay path will be set up for each positive (+) and negative (-) transition in shift register position B. The delay (chosen by wiring delay patch panel taps d0, d1, etc.) is selected by the one register and output gate combination selected by the decoder and polarity gates. The alternating polarities of the transitions are tracked by a polarity trigger which alternately selects minus and plus polarity gates, each of which may be patched for a different delay.

Delay line taps d0, d1, etc., occur at approximately 2% of a clock period. Any polarity...