Browse Prior Art Database

Dynamic Logic Circuit Family

IP.com Disclosure Number: IPCOM000080039D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Long, GB: AUTHOR

Abstract

The inverting four-phase dynamic logic buffer circuit of IBM Technical Disclosure Bulletin Vol. 15, No. 10 March 1973, pages 3164-3165, is shown as circuit 20 of the figure. By adding logical switching devices such as field-effect transistor (FET) 44 and FET 54 of circuits 40 and 50, respectively, to the basic inverter circuit 20, a whole family of logic circuits can be created. These logic circuits have the advantages of not requiring a phase time in which to make a logical decision, and of being able to provide a low-impedance output to drive a large number of standard four-phase logic circuits such as inverters 10 and 30, without padding capacitors. These circuits of the figure are especially advantageous for adding logical functions to a nearly complete large-scale integrated circuit design.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Dynamic Logic Circuit Family

The inverting four-phase dynamic logic buffer circuit of IBM Technical Disclosure Bulletin Vol. 15, No. 10 March 1973, pages 3164-3165, is shown as circuit 20 of the figure. By adding logical switching devices such as field-effect transistor (FET) 44 and FET 54 of circuits 40 and 50, respectively, to the basic inverter circuit 20, a whole family of logic circuits can be created. These logic circuits have the advantages of not requiring a phase time in which to make a logical decision, and of being able to provide a low-impedance output to drive a large number of standard four-phase logic circuits such as inverters 10 and 30, without padding capacitors. These circuits of the figure are especially advantageous for adding logical functions to a nearly complete large-scale integrated circuit design. The logical function of E = B C + D = (B + C) D has been inserted between four-phase circuits 10 and 30 of the figure, without requiring any changes to power cell timing signals phi(n-1), phi(n), and phi(n+1) of the surrounding four-phase circuits.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]