Browse Prior Art Database

Double Set Detecting Latch Circuit

IP.com Disclosure Number: IPCOM000080040D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Ligon, GC: AUTHOR

Abstract

Information can be lost if latch stages of a buffer memory are reloaded with new data before the old data is unloaded, reloaded at the same time the old data is being unloaded, or reloaded too close in time relative to the old data being unloaded, thereby not providing reliable latch operation.

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Double Set Detecting Latch Circuit

Information can be lost if latch stages of a buffer memory are reloaded with new data before the old data is unloaded, reloaded at the same time the old data is being unloaded, or reloaded too close in time relative to the old data being unloaded, thereby not providing reliable latch operation.

The circuit of the figure detects when one of these three error conditions has occurred. The +SET and -RESET inputs to the circuit of the figure correspond to load and unload times, respectively. The +GATE input acts as an enable error detection signal to detect a reset signal for unloading the buffer stages, which occurs too late relative to a second set signal for loading new data into the buffer.

Logic gates 11 and 13 compmise a master latch 12 which is set by the set input signal. The set input signal is also connected through inverter 17 to AND gate 15, to set slave latch 22 comprising gates 21 and 23 when the set signal goes down. The reset input is connected to gates 13 and 23 of the above- described latches for resetting the latches when the buffer is being unloaded.

In order to detect that the buffer is being loaded a second time before being unloaded, AND gate 25 has inputs connected to the +SET signal input and the output of OR gate 21. Thus AND gate 25 provides an output through OR gate 29 indicating an error, if a set signal is received before a reset signal has reset latch
22. AND gate 27 has a first input connected to the +...