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Diffusing Sources and Drains in Complementary Field Effect Transistors

IP.com Disclosure Number: IPCOM000080071D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 87K

Publishing Venue

IBM

Related People

Chappelow, RE: AUTHOR [+3]

Abstract

The following process for diffusing sources and drains in complementary self-aligned gate field-effect transistors (FETs) eliminates critical nitride etching, reduces etching bias and simplifies the total processing steps required.

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Diffusing Sources and Drains in Complementary Field Effect Transistors

The following process for diffusing sources and drains in complementary self-aligned gate field-effect transistors (FETs) eliminates critical nitride etching, reduces etching bias and simplifies the total processing steps required.

After P pocket 1 is formed in N substrate 2, thin layers of pyro oxide 3, silicon nitride 4 and pyro oxide 5 are deposited in the device regions 6 and 7 of Fig. 1. Source and drain windows are opened through pyro oxide and nitride layers 5 and 4. A block-off mask 8 is placed over the device area 6, as shown in Fig. 2, and the bottom pyro oxide layer 3 is etched away over the N channel FET source and drain areas 9 and 10. Arsenic is diffused into the N-channel source and drain areas. The thin oxide 3 in the P-channel source and drain areas 11 and 12 serves as a mask during the arsenic diffusion.

Reoxidation follows, with the resulting oxide being thicker over the arsenic diffused areas 9 and 10 than over the areas 11 and 12. Boron is diffused through the relatively thin oxide over areas 11 and 12, whereas the relatively thick oxide over the arsenic diffused areas 9 and 10 acts as a boron diffusion mask to produce the structure shown in Fig. 4. It is preferable that the concentration of the boron be much less than the concentration of the arsenic (Co boron , 8 x 10/19/; Co arsenic , 1 x 10/21/ at/cc), so that N+ source and drain areas 9 and 10 are unaffected by any bo...