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Polarity Hold Latch with Schottky Diode and Circuits

IP.com Disclosure Number: IPCOM000080082D
Original Publication Date: 1973-Oct-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Park, S: AUTHOR

Abstract

This circuit comprises a pair of input Schottky diode AND circuits, the outputs of which are ORed, inverted and then fed back as one input to the first AND circuits. Data is applied to an input of the second AND circuit. A set-reset line is connected directly as an input of the second AND circuit, and is coupled by way of an inverter to a second input of the first AND circuit. When the set-reset line has a logical 0 voltage level applied to it, the voltage level at the polarity hold latch output "follows" (is the same as) the data input voltage. The output is maintained even after the set-reset line goes to a logical 1 voltage level, until new data is received when the set-reset line returns to a logical 0 voltage level.

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Polarity Hold Latch with Schottky Diode and Circuits

This circuit comprises a pair of input Schottky diode AND circuits, the outputs of which are ORed, inverted and then fed back as one input to the first AND circuits. Data is applied to an input of the second AND circuit. A set-reset line is connected directly as an input of the second AND circuit, and is coupled by way of an inverter to a second input of the first AND circuit. When the set-reset line has a logical 0 voltage level applied to it, the voltage level at the polarity hold latch output "follows" (is the same as) the data input voltage. The output is maintained even after the set-reset line goes to a logical 1 voltage level, until new data is received when the set-reset line returns to a logical 0 voltage level.

Schottky diode AND circuit 1 receives a data signal at terminal D and a clock signal at terminal C, and provides an output to a first input of OR circuit 2. Schottky diode AND circuit 3 receives the polarity hold latch output signal from terminal 0 and the inverted clock signal at terminal C, and provides an output to the second input of OR circuit 2. The output from 0R circuit 2 is coupled via emitter-follower 4 and level-shifting diode-connected transistor 5 to inverter 6, whose output 0 is the output of the polarity hold latch.

When the clock signal and data signal are both high, transistor 7 of OR circuit 2 conducts and emitter-follower 4 and inverter 6 are cut off, providing an up level at...